Abstract: As for HEVC (High Efficiency Video Coding) standard decoder, high throughput rate and high
memory access volume of data serve as bottleneck problems, design of a HEVC-oriented high-efficiency sub-pixel
interpolation filtering VLSI (Very Large Scale Integration) architecture is put forward. Based on sub-pixel
interpolation algorithm in HEVC standard, an interpolation filtering VLSI architecture characterized by high
degree of parallelism and flow line is constructed. Through utilization of inversion symmetry of filter coefficients,
a reusable order-8 filter structure is designed in order to reduce area of filter hardware. On the basis of the
traditional single-input channel interpolator, a parallel-channel 8-input interpolator is designed to improve data
throughput. Experimental result indicates tha the design can meet decoding requirements of 1 920伊1 080@
30 f/ s video at a frequency of 34. 2 MHz. And this design can meet requirements of real-time transmission of
3 840伊2 160 @60 f/ s video.

Key words: dual-channel interpolation filter,  high-efficiency video coding(HEVC), architecture design, multiplexing