吉林大学学报(信息科学版) ›› 2020, Vol. 38 ›› Issue (3): 291-300.

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基于FPGA 的高分辨率科学级CMOS 相机设计

时玮淞,吕耀文   

  1. 长春理工大学光电工程学院,长春130022
  • 收稿日期:2019-12-16 出版日期:2020-05-24 发布日期:2020-06-24
  • 通讯作者: 吕耀文( 1987— ) ,男,湖北孝感人,长春理工大学讲师,硕士生导师,主要从事图像处理研究,( Tel) 86-15044100195( E-mail) lvyaowen2005@163. com。
  • 作者简介:时玮淞( 1993— ) ,男,长春人,长春理工大学硕士研究生,主要从事FPGA 开发研究,( Tel) 86-17743463981( E-mail)771931047@ qq. com; 通讯作者: 吕耀文( 1987— ) ,男,湖北孝感人,长春理工大学讲师,硕士生导师,主要从事图像处理研究,( Tel) 86-15044100195( E-mail) lvyaowen2005@163. com。
  • 基金资助:
    吉林省教育厅“十三五”科学技术研究基金资助项目( JJKH20181134KJ) ; 吉林省重点科技攻关基金资助项目
    ( 20170204048GX)

Design of High Resolution Science CMOS Camera Based on FPGA

SHI Weisong,LU Yaowen   

  1. School of Opto-Electronic Engineering,Changchun University of Science and Technology,Changchun 130022,China
  • Received:2019-12-16 Online:2020-05-24 Published:2020-06-24

摘要: 针对高分辨率科学级相机应用广泛,国内需求量大的背景,设计了基于长光辰芯公司GSENSE400 图像传
感器的国产化高分辨率科学级CMOS( Complementary Metal Qxide Semiconductor) 相机。该相机系统包括基于FPGA
( Field Programmable Gate Array) 的数据采集、控制与Camera-Link 输出设计。FPGA 主要包含SPI( Serial Peripheral
Interface) 配置模块、CMOS 时序驱动模块、数据采集模块、Camera-Link 数据转换模块以及串口通信模块。根据
CMOS 的时序逻辑,在FPGA 中实现了CMOS 驱动时序的设计。根据相机输出HDR( High-Dynamic Range) 图像的
数据量,同时为了简化FPGA 数据传输模块的设计,通过使用1 片DS90CR287 芯片,选用Camera-Link的base 模式
进行图像数据的传输,并实现串口对相机的控制。对该相机系统进行成像测试,实现了HDR 模式下连续输出
24 帧,2 048 × 2 048 像素,低读出噪声、高灵敏度、高动态范围图像,基本满足科学级成像条件的需求。

关键词: 科学级CMOS 图像传感器, 现场可编程逻辑门阵列, 高动态范围, 高分辨率

Abstract: Aiming at the background of wide application of high-resolution scientific camera and large domestic
demand,a domestic high-resolution scientific CMOS( Complementary Metal Qxide Semiconductor) camera based
on GSENSE400 image sensor of Gpixel company is designed. The camera system includes data acquisition,
control and Camera-Link output design based on FPGA( Field Programmable Gate Array) . The FPGA mainly
includes SPI ( Serial Peripheral Interface) configuration module,CMOS timing driver module,data acquisition
module,camera link data conversion module and serial communication module. According to the timing logic of
CMOS,the timing design of CMOS driver is implemented in FPGA. According to the amount of HDR( High-
Dynamic Range) image data output by the camera,in order to simplify the design of FPGA data transmission
module,using a DS90CR287 chip,the base mode of Camera-Link is selected for image data transmission,and
the serial port control of the camera is realized. The imaging test is implemented for the designed camara system.
It can output 24 frames continuously in HDR mode with 2 048 × 2 048 pixels,low readout noise,high
sensitivity,high dynamic range image,and basically meet the requirements of scientific level imaging conditions.

Key words: scientific CMOS image sensor, field programmable gate array ( FPGA) , high dynamic range, high
resolution

中图分类号: 

  • TP242