关键词: 中央处理器, 现场可编程门阵列, 实验系统, 流水线技术

Abstract: In order to solve the problem that most of the existing microelectronics major courses are based on theory and lack simulation experiments, a set of FPGA(Field Programmable Gate Array) microelectronics and integrated circuit design experiment system are designed based on RISC-V(Reduced Instruction Set Computer) CPU(Central Processing Unit). The ModelSim software compiler is used to simulate and verify, and FPGA is used as development platform to realize CPU system functions. Taking RISC-V reduced instruction set as the instruction set of the CPU and modularization as the design idea, the five-level pipeline CPU is designed from the local microprocessor to the whole. The five-level pipeline includes value, decoding, execution, memory access and write back. The system integrates software and hardware development to stimulate students' interest in learning. The experimental platform built gradually realizes the configuration and instruction set of CPU to the architecture, programming, simulation, writing and debugging of the whole CPU, enabling students to have a deep understanding of the design of integrated circuit system with FPGA, which is conducive to the study of professional theoretical courses. The design simulation content comes from the application of OBE(Outcomes- Based Education) teaching theory to integrated circuit EDA(Electronic Design Automation) course. This design method and content can also be applied to the combination of industry, university and research to improve innovation and entrepreneurship ability of students. 

Key words: central processing unit(CPU), field programmable gate array(FPGA), reduced instruction set computer(RISC-V), pipeline