基于DVB-S2标准低密度奇偶校验码译码器设计

J4 ›› 2011, Vol. 29 ›› Issue (6): 511-517.

基于DVB-S2标准低密度奇偶校验码译码器设计

王秀敏|陈豪威

中国计量学院信息工程学院|杭州 310018

出版日期:2011-11-24 发布日期:2011-12-06
作者简介:王秀敏（1963—）|女|辽宁锦州人|中国计量学院教授|硕士生导师|主要从事通信信号处理研究|（Tel）86-18968148996(Email)wxm6341@163.com。
基金资助:
国家质检总局科技计划基金资助项目（2009QK027）；浙江省科技计划优先主题重点工业基金资助项目（2010C11024）；杭州市经济开发区产学研合作基金资助项目（201002）

Design and Implementation of LDPC Decoder for DVB-S2

WANG Xiu-min|CHEN Hao-wei

College of Information Engineering,China Jiliang University,Hangzhou 310018,China

Online:2011-11-24 Published:2011-12-06

摘要/Abstract

摘要：

为解决DVB-S2标准下码长较长，译码器资源消耗较高，但速率要求较高的问题，研究了DVB-S2标准LDPC (Low Density Parity Check Code)码译码器的硬件结构。利用校验矩阵周期特性，以16 200 bit码长和06码率为例，设计了基于共享内存和后验概率累加储存的译码器结构。实验表明，该设计的LDPC码译码器共消耗24 004个逻辑单元，6 437个寄存器和448 594 bit的RAM，吞吐率达到289 Mbit/s,不仅吞吐量大，而且寄存器和内存资源的消耗也小。

关键词: DVB-S2标准;后验概率；累加存储；寄存器；共享内存

Abstract:

The hardware architecture of the DVB-S2 LDPC (Low Density Parity Check Code) code decoder is researched. According to the cyclical feature of the check matrix we have realized a decoder of the DVB-S2 LDPC code whose rate is 3/5 and length is 16 200 bit. Experiment result shows that the total consumption of the LDPC decoder are 24 004 logic cells,6 437 registers and 448 594 bits of RAM. And the throughput of is up to 289 Mbit/s.The structure of decoder using shared memory banks and writing the LLR (Log Likelihood Ratio) back to the RAM has low area and high throughput.

Key words: DVB-S2 standard;log-likelihood ratio;accumulate storage;register;shared memory

中图分类号:

TN93

王秀敏, 陈豪威. 基于DVB-S2标准低密度奇偶校验码译码器设计[J]. J4, 2011, 29(6): 511-517.

WANG Xiu-Min, CHEN Hao-Wei. Design and Implementation of LDPC Decoder for DVB-S2[J]. J4, 2011, 29(6): 511-517.

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