CDMA并行匹配滤波器的CPLD设计

CDMA并行匹配滤波器的CPLD设计

李向东¹，郭树旭¹，赵蔚²，贺蓉¹

1. 吉林大学电子科学与工程学院，长春 130023; 2. 东北师范大学广播电视学院，长春 130117

收稿日期:2002-07-30 修回日期:1900-01-01 出版日期:2003-04-26 发布日期:2003-04-26
通讯作者: 郭树旭

Implementing CDMA Parallel Matched Filter in CPLD DevicesWT

LI Xiang-dong¹, GUO Shu-xu¹, ZHAO Wei², HE Rong¹

1. College of Electronic Science and Engineering, Jilin University, Changchun 130023， China;2. School of Broadcast & Television, Northeast Normal University, Changchun 130117, China

Received:2002-07-30 Revised:1900-01-01 Online:2003-04-26 Published:2003-04-26
Contact: GUO Shu-xu

摘要/Abstract

摘要： 根据FLEX10K系列CPLD器件中查找表结构的特点和节省器件资源原则，采用折叠滤波技术和复杂可编程逻辑器件设计了CDMA并行匹配滤波器. 输入数据宽度为8位，输出数据宽度为16位，过采样率为16，通过EDA-Ⅳ型开发系统将设计硬件编程到FLEX10K芯片中，并在MAX+Plus Ⅱ开发环境中进行了仿真分析.

关键词: 复杂可编程逻辑器件, 码分多址, 匹配滤波器, 折叠滤波

Abstract: According to the LUT construction of programmable logic device (PLD) i n FLEX10K series and the saving resources principle, we designed a code division multiple access (CDMA) parallel match filter by using the folded filter and com plex programmable logic device (CPLD). The input data width is 8 bits, the outpu t data width is 16 bits, and the chip rate is 16. Using the EDA-Ⅳ development s ystem, we realized hardware programming on the FLEX10K chip, and completed simul ate analysis in the MAX+Plus Ⅱ.

Key words: complex programmable logic device, code division multip le access, matched filter, folded filter

中图分类号:

TN914.42

李向东，郭树旭，赵蔚，贺蓉. CDMA并行匹配滤波器的CPLD设计[J]. J4, 2003, 41(02): 201-205.

LI Xiang-dong, GUO Shu-xu, ZHAO Wei, HE Rong. Implementing CDMA Parallel Matched Filter in CPLD DevicesWT[J]. J4, 2003, 41(02): 201-205.