Abstract: According to the LUT construction of programmable logic device (PLD) i n FLEX10K series and the saving resources principle, we designed a code division multiple access (CDMA) parallel match filter by using the folded filter and com plex programmable logic device (CPLD). The input data width is 8 bits, the outpu t data width is 16 bits, and the chip rate is 16. Using the EDA-Ⅳ development s ystem, we realized hardware programming on the FLEX10K chip, and completed simul ate analysis in the MAX+Plus Ⅱ.

Key words: complex programmable logic device, code division multip le access, matched filter, folded filter