Abstract:

The real-time image to enlarge engine IP( Intellectual Property ) core is designed, to minimize the hardware resources of their occupation and the shortest clock cycle consumption, and to achieve the ratio of the image to enlarge. The IP core using VHDL（Very-High-Speed Integrated Circuit Hardware Description Language） language description can be integrated into a variety of display output integrated circuit chip. A simplified format D1 to XGA(Extended Graphics Array) effective method is proposed. An algorithm based on FPGA（Field Programmable Gate Array）, and the form and pipeline processing structure are also given. Experiments show that the design of image magnification system can display per second rate 65 high-quality D1 to XGA format, the same time keep a good image edge information.

Key words: field programmable gate array（FPGA）, image magnification, liner interpolation, extended graphics array(XGA)