Journal of Jilin University(Information Science Ed ›› 2014, Vol. 32 ›› Issue (1): 1-7.

    Next Articles

VLSI Implementation for Sub-Pixel Interpolation Algorithm

WANG Gang1,2, CHEN He-xin1, CHEN Mian-shu1   

  1. 1. College of Communication Engineering, Jilin University, Changchun 130022, China;2. School of Mechanical Engineering, Baicheng Normal University, Baicheng 137000, China
  • Received:2013-06-09 Online:2014-01-24 Published:2014-04-03

Abstract:

To resolve the problems of high complexity of sub-pixel interpolation operation and large access volume of storage in H.264/AVC standard, a kind of sub-pixel interpolation operation is presented. It replaces the 6 order filter with a 4 order filter which is easy for hardware implementation of sub-pixel interpolation. Based on the algorithm, a kind of 1/4 pixel precision interpolative pipeline architecture for 8×8 basic block is proposed. It is indicated by the performance analysis and filter structure that the structure can complete 32 interpolation operations of 1/2 pixel location in one clock period, which can be applied to data block with a variety of size. It has the characteristics of small area and fast speed. The experimental results show that compared with H.264 standard, the new algorithm is able to reduce space complexity by 15%, improve PSNR(Peak Signal to Noise Ratio), reduce bit rate and improve the performance of coding.

Key words: H.264, sub-pixel, very large scale integration(VLSI), space complexity, peak signal to noise ratio(PSNR), bit-rate

CLC Number: 

  • TN919.81