Abstract:  In order to optimize the performance of four-quadrant analog multiplier, to meet the application
requirements of modern analog signal processing circuit such as high-frequency and low-noise, a new low voltage
four-quadrant analog multiplier is proposed. The multiplier circuit uses the analog squarer based on MDDCC
(Modified Differential Difference Current Conveyor) as a basic module. The function of multiplying circuit is
confirmed by PSPICE ( Personal Simulation Program with Integrated Circuit Emphasis) simulations using
TSMC 0. 18 μm CMOS technology. The proposed circuit has a good linearity. The range of input voltage is
-0. 1 V ~ +0. 1 V, the -3 dB bandwidth of the proposed circuit is 451. 307 MHz and the output noise voltage is
less than 150 nV when the peak value of input voltage is 100 mV. By comparing with some available multipliers
in references, the proposed multiplier circuit has better linearity, higher cut-off frequency and reduces the output
noise voltage. The four-quadrant analog multiplier has good performance in the high frequency signal processing
system.

Key words: modified differential difference current conveyor(MDDCC),  integrated circuit, personal simulation program with integrated circuit emphasis (PSPICE) simulation, analog multiplier