Abstract:

The article designed a ROIC(Read Out Integrated Circuit) of a 320×240 FPA(Focal Plane Array）in 0.35 μm n-well CMOS(Complementary Metal\|Oxide Semiconductor) process. In order to reduce power dissipation and noise, the article proposed a kind of new single-stage CTIA(Capacitive TransImpedance Amplifier), the sample and hold circuit use a correlated double sampling structure, the CTIA used stable bias circuit. The image output time is 10 ms/frame, therefore the output speed is 100 frame/s.

Key words: infrared detector, readout circuit, correlated double sampling