Abstract: This paper presents the design of an 11-bit 1-MS/s Successive Approximation Register (SAR) Analog-to-Digital Convertor (ADC) with a set-and-down switching procedure using 0.35 μm CMOS process. The switching procedure of capacitor network is investigated. The results show that, compared with conventional 11-bit SAR ADC, the average switching energy consumption is reduced by 81.25%, and the number of unit capacitors is reduced by 50%. Post simulation results also show that Signal to Noise and Distortion Ratio (SNDR) reaches 66.6 dB and the Efficient Number of Bit (ENOB) reaches 10.7 bit. With 0.35 μm 2P3M CMOS process, the circuit layout is realized. This SAR ADC layout occupies an area of 705 μm × 412 μm.

Key words: optoelectronics and laser, analog-to-digital convertor (ADC), successive approximation register (SAR), average switching energy consumption, efficient number of bit(ENOB)