一种低功耗CMOS并行双频低噪声放大器

Abstract

Abstract: A concurrent dual-band low-noise amplifier (LNA) with single-ended input and differential output which was characterized by low power consumption was designed and implemented based on SMIC 0.18 μm 1P6M CMOS process. Using the cascode structure with inductive source degeneration, the input resistance and noise performance were optimized simultaneously at 2 different bands under power constraint, and the concurrent receive was achieved with single-ended input and differential output. The size of the LNA core circuit is 450 μm×350 μm. The LNA consumes power 8.4 mW at a power supply voltage of 1.8 V. The simulations showed that at working frequencies 1.227 GHz and 1.575 GHz, its power gains were 14.67 dB and 12.68 dB, the input return losses were-11.61 dB and-12 dB, the noise coefficients were 2.3 dB and 2.53 dB, and the input 1 dB compression points were-18.5 dBm and-14.5 dBm, respectively. The LNA can be used in concurrent dual-band global positioning system receiver for its good input match, low noise, and high linearity at dual-band.

Key words: semiconductor technology, low noise amplifier(LNA), concurrent dual-band, navigation receiver, low power consumption

CLC Number:

TN432

SHEN Jing, ZHANG Xiao-lin. Low power consumption CMOS concurrent dual-band low noise amplifier[J].吉林大学学报(工学版), 2013, 43(02): 485-490.

References

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