Journal of Jilin University(Engineering and Technology Edition) ›› 2022, Vol. 52 ›› Issue (8): 1934-1942.doi: 10.13229/j.cnki.jdxbgxb20210149

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Bipolar DC flow field⁃effect⁃transistor and its application in microfluidics

Yan-bo LI(),Yu ZHANG,Wei-yu LIU(),Qi-sheng WU,Biao WANG,Bo-bin YAO   

  1. School of Electronics and Control Engineering，Chang'an University，Xi'an 710064，China
  • Received:2021-02-24 Online:2022-08-01 Published:2022-08-12
  • Contact: Wei-yu LIU E-mail:ybl@chd.edu.cn;liuweiyu@chd.edu.cn

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Abstract:

A new method of bipolar field-effect control on DC electroosmosis（DCEO） is proposed from the perspective of electrodynamics. A mathematical model is established in thin-layer approximation and low-voltage limit to verify the feasibility of the bipolar DC-FFET structure for fluid electrodynamic manipulation at the micrometer scale. An integrated device design with two sets of side-by-side reverse polarity gate electrode pairs was used to construct a micro-device model for fully electrically driven analyte processing. By using a smaller gate voltage， an almost perfect liquid mixture can be obtained， resulting in less adverse effects at a small Dukhin number. This technology has great potential in the development of fully automatic liquid phase actuators in modern microfluidic systems.

Key words: microelectronics and solid-state electronics, bipolar DC field-effect flow control, flow field-effect-transistor, induced-charge electroosmosis

CLC Number: 

  • TN42

Fig.1

2D schematic diagrams of microfluidic device for bipolar DC field-effect electroosmosis control"

Fig.2

Effect of length of gate terminal LG on device performance in terms of dual functionalities"

Fig.3

Effect of magnitude of gate voltage VG on device performance"

Fig.4

Effect of source voltage magnitude VS on efficiency of device bifunctionality"

Fig.5

Effect of electrode separation LGG between adjacent G terminals"

Fig.6

Simultaneous pumping and mixing of microflows in device configuration with different sets of inverted B-DCFFET"

Fig.7

Effect of number of gate electrode terminal（n） on dual functionalities of integrated device configuration"

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