Abstract: We review  the  floorplanning methods for very large scale integration (VLSI), explore the significance of floorplanning in integrat
ed circuit design, and its impact on chip area, interconnect length, and design cycle. Firstly, we  review the development history of integrated circuit technology, emphasize the role of floorplanning in determining the position, size, and rotation angles of modules. Secondly, we provide a detailed introduction to four main categories of VLSI floorplanning methods: intuitive construction methods, analytical methods, iterative methods and machine learning methods. Thirdly, we discuss two commonly used  MCNC and GSRC benchmark datasets, which are crucial for testing and evaluating floorplanning methods in the VLSI design field. Finally, we summarize the research progress in the field of floorplanning and point out future research directions.

Key words: very large scale integration, floorplanning, placement, construction method, analysis method, iterative method, machine learning method