五级流水线 RISC-V 处理器软硬件协同仿真验证

吉林大学学报(信息科学版) ›› 2017, Vol. 35 ›› Issue (6): 612-616.

五级流水线 RISC-V 处理器软硬件协同仿真验证

李东泽 a , 曹凯宁 a , 曲摇明 a,b , 王富昕 b

吉林大学 a. 电子科学与工程学院; b. 计算机科学与技术学院, 长春 130012

收稿日期:2017-09-19 出版日期:2017-12-29 发布日期:2018-03-14
作者简介: 李东泽(1995— ), 男, 长春人, 吉林大学硕士研究生, 主要从事 CPU、数字信号处理等集成电路设计研究, (Tel)86-18844561092(E-mail)1418547095@ qq. com; 王富昕(1975— ), 女, 长春人, 吉林大学高级工程师, 主要从事计算机接口与组成研究, (Tel)86-13039223630(E-mail)wfx@ jlu. edu. cn。
基金资助:
吉林省发改委省级经济结构战略调整引导资金专项基金资助项目(2015Y041)

Hardware and Software Co-Simulation of RISC-V Processor with Five-Stage Pipeline

LI Dongze a , CAO Kaining a , QU Ming a,b , WANG Fuxin b

a. College of Electronic Science and Engineering; b. College of Computer Science and Technology, Jilin University, Changchun 130012, China

Received:2017-09-19 Online:2017-12-29 Published:2018-03-14

摘要/Abstract

摘要： 针对国内 RISC-V(Reduced Instruction Set Computer-Five)处理器领域的空白以及对处理器性能的优化问
题, 将开源 3 级流水线 RISC-V 处理器 VScale 扩展为 5 级流水线处理器。在对比 3 级流水线和 5 级流水线的差
异的基础上, 为 5 级流水线设计了冒险检测以及旁路单元, 解决了 5 级流水线的数据相关问题, 并为该处理器
编写外设(LCD1602、 UART)控制器, 最终在 FPGA(Field-Programmable Gate Array)开发板上实现了软硬件协同
仿真。仿真结果表明, 扩展后的处理器运行正常, 且速度比扩展前的处理器快约 30%。

关键词: 流水线, RISC-V 处理器, 数据冒险, SoC 技术

Abstract: To fill the blank of domestic RISC-V (Reduced Instruction Set Computer-Five) processor field and
optimize processor performance, the open source three-stage pipeline RISC-V processor VScale is extended to the
five-stage pipeline processor. Firstly, the difference between the three-stage and the five-stage pipeline are
compared. To solve the five-level pipeline data-related issues, the five-stage adventure detection and bypass unit
for the five-stage pipeline are designed. Peripheral (LCD1602, UART) controllers for the processor are also
implemented. The co-simulation of hardware and software are implemented on an FPGA (Field-Programmable
Gate Array)development board. Simulation results show that the extended processor is running normally, and
running faster than the original processor about 30%.

Key words: data adventure, system-on-a-chip(SoC) technology, pipeline, RISC-V processor

中图分类号:

TP368. 1

李东泽,曹凯宁,曲明,王富昕 . 五级流水线 RISC-V 处理器软硬件协同仿真验证[J]. 吉林大学学报(信息科学版), 2017, 35(6): 612-616.

LI Dongze,CAO Kaining,QU Ming,WANG Fuxin . Hardware and Software Co-Simulation of RISC-V Processor with Five-Stage Pipeline[J]. Journal of Jilin University(Information Science Ed, 2017, 35(6): 612-616.