Abstract: To fill the blank of domestic RISC-V (Reduced Instruction Set Computer-Five) processor field and
optimize processor performance, the open source three-stage pipeline RISC-V processor VScale is extended to the
five-stage pipeline processor. Firstly, the difference between the three-stage and the five-stage pipeline are
compared. To solve the five-level pipeline data-related issues, the five-stage adventure detection and bypass unit
for the five-stage pipeline are designed. Peripheral (LCD1602, UART) controllers for the processor are also
implemented. The co-simulation of hardware and software are implemented on an FPGA (Field-Programmable
Gate Array)development board. Simulation results show that the extended processor is running normally, and
running faster than the original processor about 30%.

Key words: data adventure, system-on-a-chip(SoC) technology, pipeline, RISC-V processor