Abstract:

To address the problems of low programming efficiency， high development difficulty and high Vivado HLS resource utilization in the hardware development process， a pipelined direct parallel finite impulse response filter was designed and implemented with a 127-order Hamming window using Vivado and Vitis HLS platforms. And the filtering performance of HDL FIR IP， HLS FIR IP， and XILINX FIR IP in the Vivado Simulator environment was compared. Detailed analysis was conducted on the differences in resource utilization， timing， power consumption and execution time among different implementation methods. The experimental results show that under the same conditions， the resource utilization of HLS FIR IP is reduced by 1% compared with HDL FIR IP and XILINX FIR IP， the execution time is reduced by 24.5% and 808.2% respectively， and the code size is saved by 98.5%. Based on the proposed experimental method， a comparison was made with previous work to objectively analyze the efficiency differences of different development platforms and methods under certain conditions. The results show that our design method can significantly reduce the usage of logic units and storage resources and improve the development efficiency.

Key words: astroinformatics, high-level synthesis, FIR filter, vitis HLS, verilog