面向C2VHDL编译器的基本块级指针分析算法

Abstract

Abstract: To overcome the shortcoming of existing C2VHDL compiler dealing with pointer, based on the investigation of traditional algorithm, a block-based pointer analysis algorithm was designed and realized in the ASCRA compiler, which is developed for the application of CPU-FPGA based on LLVM. Experiment results show that this algorithm can simplify the pointer analysis process, meanwhile, achieve the same precision as the flow sensitive pointer algorithm. This algorithm also can support more pointer data types than pointer reduction technology. The VHDL programs generated by ASCRA using this algorithm can achieve the same resource consumption and processing speed as the pointer reduction technology.

Key words: computer architecture, compiler for reconfigurable computing, pointer analysis algorithm, low level virtual machine (LLVM)

CLC Number:

TP312

GUO Zhen-hua, WU Yan-xia, ZHANG Guo-yin, YANG Jie, GU Guo-chang. Basic block-level pointer analysis algorithm for C2VHDL compiler[J].吉林大学学报(工学版), 2013, 43(02): 417-423.

References

[1] Li J, He H, Man H, et al. A general-purpose FPGA-based reconfigurable platform for video and image processing//Proceedings of the 6th International Symposium on Neural Networks: Advances in Neural Networks-Part Ⅲ, 2009: 299-309.

[2] Bjarne Steensgaard. Points-to analysis in almost linear time//Proceedings of the 23rd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, 1996: 32-41.

[3] Andersen L O. Program analysis and specialization for the C programming language. Copenhagen:University of Copenhagen, 1994.

[4] Choi J, Burke M, Carini P. Efficient flow-sensitive inter-procedural computation of pointer-induced aliases and side effects//In Proceedings of the 20th Annual ACM Symposium on Principles of Programming Languages, 1993: 233-245.

[5] Emami M. A practical inter-procedural alias analysis for an optimizing/paralleling C compiler. Montreal:School of Computer Science, McGill University. Montreal, Canada, 1993.

[6] Guo Zhi, Najjar Walid, Buyukkurt Betul. Efficient hardware code generation for FPGAs[J]. ACM Transactions on Architecture and Code Optimization (TACO), ACM, 2008.

[7] Gupta S, Dutt N D, Gupta R K, et al. SPARK: a high-level synthesis framework for applying parallelizing compiler transformations//Proceedings of the 16th International Conference on VLSI Design (VLSI), Paul Chow, 2003: 461-466.

[8] Alex Jones, Debabrata Bagchi, Satrajit Pal. PACT HDL: A C Compiler Targeting ASICs and FPGAs with Power and Performance Optimizations//Proceedings of the 2002 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, 2002: 188-197.

[9] Séméria L, Micheli G De. SPC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C//In Proc Int Conf Computer-Aided Design ICCAD’98, San Jose, CA,1998:321-326.

[10] Lau D, Pritchard O, Molson P. Automated generation of hardware accelerators with direct memory access from ANSI/ISO Standard C Functions//FCCM’06,2006:45-54.

[11] Franke B, O'Boyle M F. A complete compiler approach to auto-parallelizing C programs for multi-DSP systems[J]. IEEE Transactions on Parallel and Distributed Systems, 2005: 234-245.

[12] Hardekopf B, Lin C. Semi-sparse flow-sensitive pointer analysis//In POPL'09: Proceedings of the 36th annual ACM SIGPLAN-SIGACT symposium on Principle of Programming Languages, New York, NY, USA, 2009: 226-238.

[13] 王甜甜,苏小红,马培军. 程序标准化转换中的指针分析算法研究[J]. 电子学报,2009, 37(5):1104-1108. Wang Tian-tian, Su Xiao-hong, Ma Pei-jun. Research on pointer analysis algorithm for program standardization[J]. Chinese Journal of Electronics. 2009, 37(5): 1104-1108.

[14] 吴艳霞,顾国昌,孙延腾,等. 面向应用的可重构编译ASCRA[J]. 计算机科学与探索,2011, 5(3): 267-279. Wu Yan-xia, Gu Guo-chang, Sun Yan-teng, et al. Application-specific compiler for reconfigurable architecture ASCRA[J]. Journal of Frontiers of Computer Science and Technology, 2011, 5(3): 267-279.

[15] Cheng Ben-Chung, Hwu Wen-Mei W. Modular interprocedural pointer analysis using access paths: design, implementation, and evaluation//In proceedings of the ACM SIGPLAN'00 Conference on Programming Language Design and Implementation. ACM Press, 2000: 57-69.

Metrics

Viewed

Full text

Abstract

Cited

Shared

Discussed

Comments

Recommended 0

No Suggested Reading articles found!

Basic block-level pointer analysis algorithm for C2VHDL compiler

RICH HTML

PDF (PC)

Abstract

Cite this article

share this article

References

Related Articles 5

Metrics

Comments

Recommended 0

[1]	DONG Yue-li, GUO Quan, SUN Bin, KANG Ling. Dynamic task migration optimization for molecule docking [J]. 吉林大学学报(工学版), 2015, 45(4): 1253-1259.
[2]	ZHANG Qing-feng,XU Jing,LI Shan-shan. Interaction-aware parallel query scheduling strategy [J]. 吉林大学学报(工学版), 2015, 45(1): 252-260.
[3]	REN Xiang-long, GAO De-yuan, FAN Xiao-ya, AN Jian-feng. Analysis of delay bounds for NoC based on improved asymmetric multi-channel router [J]. 吉林大学学报(工学版), 2014, 44(3): 782-787.
[4]	LIU Yan-heng, ZHOU Peng, WANG Jian, DENG Jun-yi. Context-aware adaptive middleware in vehicular network [J]. 吉林大学学报(工学版), 2013, 43(02): 410-416.
[5]	HAN Li-min, GAO De-yuan, FAN Xiao-ya, SHI Li-wen, AN Jian-feng. Reusable data predicting mechanism for shared last level Cache in chip multi-processor [J]. , 2012, (06): 1505-1509.