吉林大学学报(工学版) ›› 2017, Vol. 47 ›› Issue (2): 591-600.doi: 10.13229/j.cnki.jdxbgxb201702034

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Lower power dynamic scheduling algorithm for sporadic tasks based on balance factor

DENG Chang-yi1, 2, GUO Rui-feng1, ZHANG Yi-wen3, WANG Hong-liang1   

  1. 1.Shenyang Institute of Computing Technology, Chinese Academy of Sciences, Shenyang 110168, China;
    2.University of Chinese Academy of Sciences, Beijing 100039, China;
    3.College of Computer Science and Technology, Huaqiao University, Xiamen 361021, China
  • Received:2015-11-20 Online:2017-03-20 Published:2017-03-20

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Abstract: In order to reduce power consumption in real-time system, a Lower Power Dynamic Scheduling Algorithm for Sporadic Task (LP-DSAFST) is proposed based on balancing factor. The LP-DSAFST algorithm is divided into two phases. The first phase scales the processor speed according to the workload of the release task. The second phase dynamically updates the processor speed by the remaining slack time of the high-priority task and when the process has no task execution, the balancing factor is used to determine whether the processor enters into sleep mode with DPM technology. Experimental results show that the proposed LP-DSAFST algorithm outperforms the existing Dynamic Voltage Scaling for Sporadic Tasks (DVSST) and Dynamic Sporadic Task Lower Power Scheduling (DSTLPS) algorithms, which can save 10.3% ~ 62.5% and 5.4% ~ 20.6% energy consumption.

Key words: computer systems organization, dynamic voltage scaling, critical speed, real-time system, balance factor

CLC Number: 

  • TP316
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