Abstract:

A packet decoding method for convolutional codes is proposed based on Field Programmable Gate Array (FPGA). It overcomes the shortcomings of larger consumption of hardware and lower decoding speed with the traditional Viterbi method. By this method the data to be decoded are divided into several groups first, and the mutual influences among the groups are fully considered. Then the data of different groups are decoded respectively. The final decoding output is obtained after integrative consideration of the decoding results of each data group. Investigation shows that, with the same feedback depth, the proposed decoding method can save hardware consumption and increase the decoding speed in comparison with the traditional Viterbi decoding method.

Key words: communication engineering, FPGA, convolutional code, packet decoding