吉林大学学报(工学版) ›› 2015, Vol. 45 ›› Issue (5): 1624-1630.doi: 10.13229/j.cnki.jdxbgxb201505035

Previous Articles     Next Articles

Latency equalization of memory access in network-chips

LI Yang1, 2, CHEN Xiao-wen3, ZHAO Xiao-hui1, YANG Yong2   

  1. 1.College of Communication Engineering, Jilin University, Changchun 130022,China;
    2.School of Electronics and Information Engineering, Changchun University of Science and Technology, Changchun 130022, China;
    3.College of Computer, National University of Defense Technology, Changsha 410073, China
  • Received:2015-02-14 Online:2015-09-01 Published:2015-09-01

RICH HTML

0   

PDF (PC)

261

Abstract: A novel arbitration technique for memory access packets is proposed, which is based on the round-trip latency prediction. First, the congestion information in the subsequent path of memory access packets is used to predict the waiting latencies of the memory access packets in the future, and then the round-trip latencies are calculated. Second, the predicted round-trip latencies are used to decide the arbitration for the memory access packets contending for the same link. The proposed technique is designed and implemented in the routers of mesh-based NoCs. Experimental results show that, under different network sizes and packet injection rates, compared with the classic Round-Robin arbitration mechanism, the proposed technique can greatly reduce the maximum latency, the average latency and the latency standard deviation of on-chip memory accesses, and it is proved to achieve better latency equalization of memory access.

Key words: communication technology, network-on-chip (NOC), memory access latency, many-core architectures, arbitration technique, equalization

CLC Number: 

  • TN91
[1] Horowitz M, Dally W. How scaling will change processor architecture[C]∥International Solid-State Circuits Conference (ISSCC'04), San Francisco, US, Digest of Technical Papers, 2004:132-133.
[2] Borkar S. Thousand core chips: a technology perspective[C]∥Proceedings of the 44th Design Automation Conference (DAC'07), San Diego, US, 2007:746-749.
[3] Owens J D, Dally W J. Research challenges for on-chip interconnection networks[J]. IEEE Micro, 2007, 27(5):96-108.
[4] Marinissen E, Prince B, Keltel-Schulz D, et al. Challenges in embedded memory design and test[C]∥Proceedings of Design, Automation and Test in Europe Conference (DATE'05), Munich, Germany, 2005:722-727.
[5] Genius D. Measuring memory access latency for software objects in a NUMA system-on-chip architecture[C]∥Proceedings of the 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCo -SoC), Darmstadt, Germany, 2013: 1-8.
[6] Majo Z, Gross T R. Memory system performance in a NUMA multicore multi-processor[C]∥Proceedings of the 4th Annual International Conference on Systems and Storage, Haifa, Israel, 2011: 1-10.
[7] Mutlu O, Moscibroda T. Stall-time fair memory access scheduling for chip multiprocessor[C]∥Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Chicago, US, 2007: 146-160.
[8] Daneshtalab M, Ebrahimi M, Plosila J, et al. CARS: congestion-aware request scheduler for network interfaces in NoC-based manycore systems[C]∥Proceedings of Design, Automation and Test in Europe Conference (DATE'13), Grenoble, France, 2013:1048-1051.
[9] Kim D, Yoo S, Lee S. A network congestion-aware memory controller[C]∥Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, 2010:257-264.
[10] Zhang G, Wang H, Chen X, et al. Fair memory access scheduling for quality of service guarantees via service curves[C]∥Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, Madrid, Spain, 2012: 174-181.
[11] Jang W, Pan D. An SDRAM-aware router for networks-on-chip[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010, 29(10): 1572-1585.
[12] Pimpalkhute T, Pasricha S. Noc scheduling for improved application-aware and memory-aware transfers in multi-core systems[C]∥Proccedings of the 27th International Conference on VLSI Design and the 13th International Conference on Embedded Systems, Mubai ,India,2014:234-239.
[13] 刘胜, 陈书明, 尹亚明, 等. 片上网络延时差异对存储系统公平性的影响及对策[J]. 计算机学报,2011,34(8):1500-1508. Liu Sheng,Chen Shu-ming,Yin Ya-ming,et al.The effect of NoC latency difference on the fairness of memory systems and a strategy[J].Chinese Journal of Computers,2011,34(8):1500-1508.
[14] Sharifi A, Kultursay E, Kandemir M, et al. Addressing end-to-end memory access latency in noc-based multicores[C]∥Proccedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'12), Vancouver, BC, Canada, 2012:294-304.
[15] Dally W J. Virtual-channel flow control[J]. IEEE Transactions on Parallel and Distributed Systems, 1992, 3(2):194-205.
[16] Kumar A, Peh L, Kundu P, et al. Express virtual channels: towards the ideal interconnection fabric[C]∥Proceedings of the 34th Annual International Symposium on Computer Architecture (ISCA'07), San, Diego, US, 2007:150-161.
[1] ZHOU Yan-guo,ZHANG Hai-lin,CHEN Rui-rui,ZHOU Tao. Two-level game approach based resource allocation scheme in cooperative networks [J]. Journal of Jilin University(Engineering and Technology Edition), 2018, 48(6): 1879-1886.
[2] SUN Xiao-ying, HU Ze-zheng, YANG Jin-peng. Assessment method of electromagnetic pulse sensitivity of vehicle engine system based on hierarchical Bayesian networks [J]. 吉林大学学报(工学版), 2018, 48(4): 1254-1264.
[3] DONG Ying, CUI Meng-yao, WU Hao, WANG Yu-hou. Clustering wireless rechargeable sensor networks charging schedule based on energy prediction [J]. 吉林大学学报(工学版), 2018, 48(4): 1265-1273.
[4] MOU Zong-lei, SONG Ping, ZHAI Ya-yu, CHEN Xiao-xiao. High accuracy measurement method for synchronous triggering pulse transmission delay in distributed test system [J]. 吉林大学学报(工学版), 2018, 48(4): 1274-1281.
[5] DING Ning, CHANG Yu-chun, ZHAO Jian-bo, WANG Chao, YANG Xiao-tian. High-speed CMOS image sensor data acquisition system based on USB 3.0 [J]. 吉林大学学报(工学版), 2018, 48(4): 1298-1304.
[6] CHEN Rui-rui, ZHANG Hai-lin. Performance analysis of 3D millimeter wave communications [J]. 吉林大学学报(工学版), 2018, 48(2): 605-609.
[7] ZHANG Chao-yi, LI Jin-hai, YAN Yue-peng. Improved Tong detection algorithm with double thresholds [J]. 吉林大学学报(工学版), 2018, 48(2): 610-617.
[8] GUAN Ji-shi, SHI Yao-wu, QIU Jian-wen, SHAN Ze-biao, SHI Hong-wei. New algorithm to estimate characteristic exponent of α-stable distribution [J]. 吉林大学学报(工学版), 2018, 48(2): 618-624.
[9] LI Wei, LI Ya-jie. Satisfactory integrated design between failure accommodation and communication for non-uniform transmission networked control system under discrete event-triggered communication scheme [J]. 吉林大学学报(工学版), 2018, 48(1): 245-258.
[10] SUN Xiao-ying, WANG Zhen, YANG Jin-peng, HU Ze-zheng, CHEN Jian. Electromagnetic susceptibility assessment of electronic throttle based on Bayesian network [J]. 吉林大学学报(工学版), 2018, 48(1): 281-289.
[11] WU Wei, WANG Shi-gang, ZHAO Yan, WEI Jian, ZHONG Cheng. Hexagonal elemental image array generation [J]. 吉林大学学报(工学版), 2018, 48(1): 290-294.
[12] YUAN Jian-guo, ZHANG Xi-ruo, QIU Piao-yu, WANG Yong, PANG Yu, LIN Jin-zhao. Non-iterative phase noise suppression algorithm utilizing cyclic prefix in OFDM systems [J]. 吉林大学学报(工学版), 2018, 48(1): 295-300.
[13] WANG Jin-peng, CAO Fan, HE Xiao-yang, ZOU Nian-yu. Multi carrier system joint receiving method based on MAI and ICI [J]. 吉林大学学报(工学版), 2018, 48(1): 301-305.
[14] SHI Wen-xiao, SUN Hao-ran, WANG Shao-bo. Joint channel allocation and routing algorithm in wireless mesh network [J]. 吉林大学学报(工学版), 2017, 47(6): 1918-1925.
[15] JIANG Lai-wei, SHA Xue-jun, WU Xuan-li, ZHANG Nai-tong. Novel joint user association and resource allocation method in LTE-A HetNets [J]. 吉林大学学报(工学版), 2017, 47(6): 1926-1932.
Viewed
Full text


Abstract

Cited
  Shared   
  Discussed   
No Suggested Reading articles found!
Copyright © Journal of Jilin University(Engineering and Technology Edition), All Rights Reserved.
Tel: +86-431-85095297　Fax: +86-431-85094074　E-mail: xbgxb@jlu.edu.cn
Powered by Beijing Magtech Co. Ltd