吉林大学学报(工学版) ›› 2015, Vol. 45 ›› Issue (5): 1624-1630.doi: 10.13229/j.cnki.jdxbgxb201505035

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Latency equalization of memory access in network-chips

LI Yang1, 2, CHEN Xiao-wen3, ZHAO Xiao-hui1, YANG Yong2   

  1. 1.College of Communication Engineering, Jilin University, Changchun 130022,China;
    2.School of Electronics and Information Engineering, Changchun University of Science and Technology, Changchun 130022, China;
    3.College of Computer, National University of Defense Technology, Changsha 410073, China
  • Received:2015-02-14 Online:2015-09-01 Published:2015-09-01

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Abstract: A novel arbitration technique for memory access packets is proposed, which is based on the round-trip latency prediction. First, the congestion information in the subsequent path of memory access packets is used to predict the waiting latencies of the memory access packets in the future, and then the round-trip latencies are calculated. Second, the predicted round-trip latencies are used to decide the arbitration for the memory access packets contending for the same link. The proposed technique is designed and implemented in the routers of mesh-based NoCs. Experimental results show that, under different network sizes and packet injection rates, compared with the classic Round-Robin arbitration mechanism, the proposed technique can greatly reduce the maximum latency, the average latency and the latency standard deviation of on-chip memory accesses, and it is proved to achieve better latency equalization of memory access.

Key words: communication technology, network-on-chip (NOC), memory access latency, many-core architectures, arbitration technique, equalization

CLC Number: 

  • TN91
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