关键词: 计算机系统结构, 关键路径, 层次设计, 定时分析, 通路敏化

Abstract: To address the problem of low accuracy of timing characterization caused by the large scale of VLSI circuits, a new timing characterization method to improve the accuracy of timing models in hierarchical circuits is proposed. The concepts of the local false path and global false path are introduced to the method. Experiment results show that, for some benchmark circuits with thousands of gates, this method is capable to generate timing models with very accurate path delay. Results also show that, without resorting intensive search-based or symbolic techniques to account for the circuit functionality, this method can provide correct calculation results and eliminate the vast majority of the false paths caused by mode connections in hierarchical design. This ensures the accuracy of circuit delay.

Key words: computer system organization, critical path, hierarchical design, timing analysis, path sensitization