关键词: 电子技术, 测试平台, 时钟抖动, 相位偏差, 伪随机测试

Abstract: A method to design a random clock error test bench in verilog was introduced which combines the simulating verification of the video mode detector. This method utilizes and improves the random number generation function provided by verilog to generate a set of random vectors, which approximately obey Gauss distribution. Simulation on the module can be carried out by imitating the real timing of the input signals. Simulation results indicate that the proposed method can effectively verify the impacts of the clock jitter and the random phase skew between signals on the design. The method can be used in other random tests.

Key words: electronics, test bench, clock jitter, phase skew, pseudorandom test