一种低功耗CMOS并行双频低噪声放大器

吉林大学学报(工学版) ›› 2013, Vol. 43 ›› Issue (02): 485-490.

一种低功耗CMOS并行双频低噪声放大器

申晶, 张晓林

北京航空航天大学电子信息工程学院, 北京 100191

收稿日期:2012-02-23 出版日期:2013-03-01 发布日期:2013-03-01
作者简介:申晶(1987-),女,博士研究生.研究方向:导航接收机和集成电路.E-mail:shenjing87@gmail.com
基金资助:
国防科工委民用航天专项项目;北京市重点学科基金项目(XK100060525).

Low power consumption CMOS concurrent dual-band low noise amplifier

SHEN Jing, ZHANG Xiao-lin

School of Electronic and Information Engineering, Beijing University of Aeronautics and Astronautics, Beijing 100191, China

Received:2012-02-23 Online:2013-03-01 Published:2013-03-01

摘要/Abstract

摘要： 基于SMIC 0.18μm 1P6M CMOS工艺,设计实现了一种低功耗单端输入转差分输出的并行双频低噪声放大器。采用带有源级电感负反馈的共源共栅结构,在功耗限制下在双频段对输入阻抗和噪声性能同时进行优化,实现并行接收,并具有单端输入转差分输出的功能。该低噪声放大器核心电路尺寸为450 μm×350 μm。仿真表明,低噪声放大器(LNA)在1.227 GHz和1.575 GHz工作频率处的输入回波损耗分别为-11.61 dB和-12 dB,功率增益分别为14.67 dB和12.68 dB,噪声系数分别为2.3 dB和2.53 dB,输入l dB压缩点分别为-18.5 dBm和-14.5 dBm。在1.8 V电源电压下,功耗仅为8.4 mW,可用于航空航天领域的电子系统中。

关键词: 半导体技术, 低噪声放大器, 并行双频, 导航接收机, 低功耗

Abstract: A concurrent dual-band low-noise amplifier (LNA) with single-ended input and differential output which was characterized by low power consumption was designed and implemented based on SMIC 0.18 μm 1P6M CMOS process. Using the cascode structure with inductive source degeneration, the input resistance and noise performance were optimized simultaneously at 2 different bands under power constraint, and the concurrent receive was achieved with single-ended input and differential output. The size of the LNA core circuit is 450 μm×350 μm. The LNA consumes power 8.4 mW at a power supply voltage of 1.8 V. The simulations showed that at working frequencies 1.227 GHz and 1.575 GHz, its power gains were 14.67 dB and 12.68 dB, the input return losses were-11.61 dB and-12 dB, the noise coefficients were 2.3 dB and 2.53 dB, and the input 1 dB compression points were-18.5 dBm and-14.5 dBm, respectively. The LNA can be used in concurrent dual-band global positioning system receiver for its good input match, low noise, and high linearity at dual-band.

Key words: semiconductor technology, low noise amplifier(LNA), concurrent dual-band, navigation receiver, low power consumption

中图分类号:

TN432

申晶, 张晓林. 一种低功耗CMOS并行双频低噪声放大器[J]. 吉林大学学报(工学版), 2013, 43(02): 485-490.

SHEN Jing, ZHANG Xiao-lin. Low power consumption CMOS concurrent dual-band low noise amplifier[J]. 吉林大学学报(工学版), 2013, 43(02): 485-490.

参考文献

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[4] Shim Y, Kim C W, Lee J, et al. Design of full band UWB common-gate LNA[J]. IEEE Microwave and Wireless Components Letters, 2007, 17(10): 721-723.

[5] Wang R L, Lin M C, Yang C F, et al. A lV 3.1-10.6 GHz full-band cascoded UWB LNA with resistive feedback//IEEE Conference on Electron Devices and Solid-State Circuits.Taiwan: IEEE, 2007.

[6] Hashemi H, Hajimiri A. Concurrent dual-band CMOS low noise amplifiers and receiver architectures//Symposium on VLSI Circuits Digest of Technical Papers. Japan: IEEE, 2001.

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[8] Lee T H. The Design of CMOS Radio-frequency Integrated Circuits[M]. 2nd ed. Beijing: Publishing House of Electronics Industry, 2006.

[9] Nguyen T K, Kim C H, Ihm G J, et al. CMOS low-noise amplifier design optimization techniques[J]. IEEE Transactions on Microwave Theory and Techniques, 2004, 52(5): 1433-1442.

[10] Lian L L, Noh N M, Mustaffa M T, et al. A dual-band LNA with 0.18-μm CMOS switches//2011 IEEE Regional Symposium on Micro and Nanoelectronics (RSM). Kota Kinabalu: IEEE,2011.

[11] 苏俊. GPS、北斗双模用户机双频段低噪声放大器设计. 北京:北京交通大学电子信息工程学院,2009. Su Jun. Design of dual-band LNA for GPS and Beidou dual-mode receiver. Beijing: School of Electronic and Information Engineering, Beijing Jiaotong University,2009.

[12] Amor M B, Fakhfakh A, Mnif H, et al. Dual band CMOS LNA design with current reuse topology//International Conference on Design and Test of Integrated Systems in Nanoscale Techenology. Tunis: IEEE, 2006.

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