基于Vitis HLS的FIR滤波器设计及其性能分析

doi:10.13229/j.cnki.jdxbgxb.20230566

吉林大学学报(工学版) ›› 2025, Vol. 55 ›› Issue (3): 1072-1081.doi: 10.13229/j.cnki.jdxbgxb.20230566

• 计算机科学与技术 • 上一篇

基于Vitis HLS的FIR滤波器设计及其性能分析

张海龙^1,^2,^3,⁴(),杜旭^1,²,张萌^1,²,张亚州^1,²,王杰^1,⁴,冶鑫晨^1,⁴,王万琼¹,李嘉¹,吴涵^1,²,张婷^1,²

^1.中国科学院新疆天文台，乌鲁木齐 830011
^2.中国科学院大学，北京 100049
^3.中国科学院射电天文重点实验室，南京 210008
^4.国家天文科学数据中心，北京 100101

收稿日期:2023-06-06 出版日期:2025-03-01 发布日期:2025-05-20
作者简介:张海龙（1980-），男，正高级工程师，博士.研究方向：数据密集型研究.E-mail：zhanghailong@xao.ac.cn
基金资助:
国家重点研发计划项目(2021YFC2203502);国家自然科学基金项目(12173077);新疆维吾尔自治区天山创新团队计划项目(2022D14020);“天山英才”培养计划项目(2022TSYCCX0095);中国科学院科研仪器设备研制项目(PTYQ2022YZZD01);国家天文科学数据中心;中国科学院天文台站设备更新及重大仪器设备运行专项经费;新疆维吾尔自治区自然科学基金项目(2022D01A360);中国科学院“西部之光”人才培养引进计划项目(2022-XBQNXZ-012)

Filter design and performance analysis based on vitis HLS

Hai-long ZHANG^1,^2,^3,⁴(),Xu DU^1,²,Meng ZHANG^1,²,Ya-zhou ZHANG^1,²,Jie WANG^1,⁴,Xin-chen YE^1,⁴,Wan-qiong WANG¹,Jia LI¹,Han WU^1,²,Ting ZHANG^1,²

^1.Xinjiang Astronomical Observatory，Chinese Academy of Sciences，Urumqi 830011，China
^2.University of；Chinese Academy of Sciences，Beijing 100049，China
^3.Key Laboratory of Radio Astronomy，Chinese Academy of；Sciences，Nanjing 210008，China
^4.National Astronomical Data Center，Beijing 100101，China

Received:2023-06-06 Online:2025-03-01 Published:2025-05-20

摘要/Abstract

摘要：

针对硬件开发过程中存在编程效率低、开发难度高及Vivado HLS资源使用率高等问题，利用Vivado及Vitis HLS平台设计并实现了基于127阶Hamming窗的流水线式直接型并行结构有限冲激响应滤波器，在Vivado Simulator环境下对比了HDL FIR IP、HLS FIR IP与XILINX FIR IP的滤波表现，详细分析了不同实现方式在资源使用率、时序、功耗、执行时间等方面的差异。实验结果表明：在相同条件下HLS FIR IP相较HDL FIR IP及XILINX FIR IP的资源使用率降低了1%，执行时间分别降低了24.5%、808.2%，且代码量节省了98.5%。以本文实验方法为基础与前人工作进行对比，客观分析了在一定条件下不同开发平台及方式的效率差异，结果表明本文设计方法可显著降低逻辑单元和存储资源的使用率，并提升开发效率。

关键词: 天文信息技术, 高层次综合, FIR滤波器, Vitis HLS, Verilog

Abstract:

To address the problems of low programming efficiency， high development difficulty and high Vivado HLS resource utilization in the hardware development process， a pipelined direct parallel finite impulse response filter was designed and implemented with a 127-order Hamming window using Vivado and Vitis HLS platforms. And the filtering performance of HDL FIR IP， HLS FIR IP， and XILINX FIR IP in the Vivado Simulator environment was compared. Detailed analysis was conducted on the differences in resource utilization， timing， power consumption and execution time among different implementation methods. The experimental results show that under the same conditions， the resource utilization of HLS FIR IP is reduced by 1% compared with HDL FIR IP and XILINX FIR IP， the execution time is reduced by 24.5% and 808.2% respectively， and the code size is saved by 98.5%. Based on the proposed experimental method， a comparison was made with previous work to objectively analyze the efficiency differences of different development platforms and methods under certain conditions. The results show that our design method can significantly reduce the usage of logic units and storage resources and improve the development efficiency.

Key words: astroinformatics, high-level synthesis, FIR filter, vitis HLS, verilog

中图分类号:

TP301.6

张海龙,杜旭,张萌,张亚州,王杰,冶鑫晨,王万琼,李嘉,吴涵,张婷. 基于Vitis HLS的FIR滤波器设计及其性能分析[J]. 吉林大学学报(工学版), 2025, 55(3): 1072-1081.

Hai-long ZHANG,Xu DU,Meng ZHANG,Ya-zhou ZHANG,Jie WANG,Xin-chen YE,Wan-qiong WANG,Jia LI,Han WU,Ting ZHANG. Filter design and performance analysis based on vitis HLS[J]. Journal of Jilin University(Engineering and Technology Edition), 2025, 55(3): 1072-1081.

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参考文献 15

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参数	HDL FIR IP	HLS FIR IP	XILINX FIR IP
最差负时序裕量/ns	8.79	4.582	9.728
最差保持时序裕量/ns	0.022	0.024	0.011
最差脉冲宽度时序裕量/ns	5.677	5.677	5.677
时序裕量之和/ns	14.489	10.283	15.416

	HDL FIR IP	HLS FIR IP	XILINX FIR IP
片上总功耗/W	1.243	1.228	1.137
预计结温/℃	26.0	26.0	26.0
热裕度/℃	74.0	74.0	74.0
有效热阻/（℃·W^-1）	0.8	0.8	0.8

方法	HDL语言	HLS工具	比较项	资源使用率之和/%	时序裕量之和或时钟速度	总功耗/W	执行时间	编程时间或代码行
Zwagerman^［13］	Verilog	Vivado HLS 2013.4	图像滤波	HDL：129.8 HLS：133.1	HDL：200 MHz HLS：181 MHz	-	-	HDL：33 h HLS：15 h
Roberto Millón	VHDL	Vivado HLS 2019.1	Sobel 边缘检测	HDL：2.9 HLS：8.4	-	-	HDL：58 ms HLS：82.9 ms	HDL：493LOC HLS：90LOC
Srilakshmi等	VHDL	Vitis HLS N/A	CNN卷积层	HDL：0.7 HLS：2.4	-	-	-	-
本文	Verilog	Vitis HLS 2022.1	FIR 滤波器	HDL：19.83 HLS：18.86 XILINX：19.85	HDL：14.5 ns HLS：10.3 ns XILINX：15.4 ns	HDL：1.243 HLS：1.228 XILINX：1.137	HDL：122 ns HLS：98 ns XILINX：890 ns	HDL：2397LOC HLS：36LOC

基于Vitis HLS的FIR滤波器设计及其性能分析

Filter design and performance analysis based on vitis HLS

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