吉林大学学报(工学版) ›› 2018, Vol. 48 ›› Issue (3): 968-976.doi: 10.13229/j.cnki.jdxbgxb20170150

• Orginal Article • Previous Articles    

Design of pipeline analog digital converter used for CMOS image sensors

CHEN Ming1,2, CHEN Jie1,2, XIAO Jing-bo1,2   

  1. 1.Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;
    2.School of Microelectronics, University of Chinese Academy of Sciences, Beijing 100029,China
  • Received:2017-02-23 Online:2018-05-20 Published:2018-05-20

Abstract: This paper presents a low power pipeline Analog-to-Digital Converter (ADC) used in CMOS image sensor. We propose a new fully differential ring amplifier, and employ a SAR ADC to assist the pipeline architecture. Comparing with conventional Operational Transconductance Amplifier (OTA), the proposed amplifier has higher energy-efficiency. This design is implemented in 0.18 μm 1P5M 1.8 V/3.3 V process. The post-simulation results indicate that it can achieve a maximum differential nonlinearity of +0.58 LSB/-0.33 LSB, a maximum integral nonlinearity of +0.55 LSB/-0.57 LSB, Spurious-Free Dynamic Range (SFDR) of 64.9 dB and Signal-to-Noise and Distortion Ratio (SNDR) of 57.8 dB for a 19.94 MHz input at sampling rate. The total power dissipation of ADC core is 3.78 mW, the FoM of ADC is 148 fJ/conv-step.

Key words: semiconductor technology, CMOS image sensor, pipeline ADC, ring amplifier, SAR

CLC Number: 

  • TN43
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