Journal of Jilin University(Engineering and Technology Edition) ›› 2019, Vol. 49 ›› Issue (6): 2051-2057.doi: 10.13229/j.cnki.jdxbgxb20180480

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Acceleration platform for face detection and recognition based on field⁃programmable gate array

You ZHOU1,2(),Sen YANG1,2,Da-lin LI1,2,Chun-guo WU1,2,Yan WANG1,2,Kang-ping WANG1,2()   

  1. 1. College of Computer Science and Technology, Jilin University, Changchun 130012, China
    2. Key Laboratory of Symbol Computation and Knowledge Engineering of Ministry of Education, Jilin University, Changchun 130012, China
  • Received:2018-05-15 Online:2019-11-01 Published:2019-11-08
  • Contact: Kang-ping WANG E-mail:zyou@jlu.edu.cn;wangkp@jlu.edu.cn

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Abstract:

A heterogeneous computing technique based on Field－Programmable Gate Array (FPGA) is proposed in this paper. The Viola-Jones face detection algorithm is accelerated based on concurrent and pipelining methods to improve data throughput and increase the parallelism of cascaded classifiers and convolution neural network is accelerated by concurrent convolution and pipelined feature maps. The experimental results show that the hardware platform achieves a speedup of 2.9 times compared with the software platform.

Key words: computer application, face detection, face recognition, convolution neural network, field programmable gate array（FPGA） algorithm, algorithm hardware

CLC Number: 

  • TP338

Fig.1

Haar feature map"

Fig.2

Original image and integral image"

Fig.3

Schematic diagram of cascade classifier"

Fig.4

Schematic diagram of convolutionalneural network"

Fig.5

Schematic diagram of integral imageacceleration"

Fig.6

Throughput capacity of each STAGE incascade classifier"

Fig.7

Schematic diagram of cascade classifieracceleration"

Fig.8

Convolution calculation procedure"

Fig.9

Schematic diagram of accelerating platform diagram"

Fig.10

Detection recognition results"

Table 1

Hardware resource list"

硬件名称 硬件型号
PC主机CPU型号 Inter(R) CPU i5 2310,2.9 GHz,4核
PC主机内存 8 GB
PC主机操作系统 Ubuntu16.04 64位
GPU GEFORCE GTX 1060
FPGA型号 XILINX KCU105

Table 2

Software resource list"

软件名称 软件版本
Opencv V3.4
Vivado HLS V16.04
Vivado V16.04
Keras V2.4

Table 3

Face recognition module network structure"

层名称 输入/出尺寸 参数量
input(Input) (None, 28, 28, 1) 0
conv2d_1(Conv2D) (None, 26, 26, 8) 80
conv2d_2(Conv2D) (None, 24, 24, 16) 1 168
Norm(Norm) (None, 24, 24, 16) 0
mp2d_1(MP2d） (None, 12, 12, 16) 0
conv2d_3(Conv2D) (None, 10, 10, 16) 2 320
Dropout_1(Dropout) (None, 10, 10, 16) 0
flatten_1(Flatten) (None, 1600) 0
dense_1(Dense) (None,32) 51 232
dropout_2(Dropout) (None,32) 0
dense_2 (Dense) (None,10) 330

Table 4

FPGA resource usage"

逻辑资源 使用资源 总资源 使用率/%
LUT 195 044 242 400 76.39
REGISTER 352 370 484 800 64.43
DSP 376 1 920 14.95
BRAM 556 600 89.17

Table 5

Comparison of hardware andsoftware platforms"

人脸数 CPU平台 CPU+FPGA平台 加速比/倍
t/ms f 0/(帧·s-1) t/ms f 0/(帧·s-1)
1 125.62 7.96 43.08 23.81 2.991
2 129.19 7.74 44.07 22.69 2.931
4 136.79 7.31 45.55 21.95 3.002
8 142.24 7.03 48.01 20.83 2.963

Fig.11

Comparison of time and frame number ofhardware and software platform"

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