Journal of Jilin University(Engineering and Technology Edition) ›› 2024, Vol. 54 ›› Issue (8): 2282-2287.doi: 10.13229/j.cnki.jdxbgxb.20230340

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Optimization of cache scheduling algorithm for embedded multi-core system

Peng WANG1,2(),Guo-dong YANG1,3   

  1. 1.Key Laboratory of Civil Aviation Aircraft Airworthiness Certification Technology，Civil Aviation University of China，Tianjin 300300，China
    2.Civil Aviation University of China，College of Safety Science and Engineering，Tianjin 300300，China
    3.Civil Aviation University of China，Sino-European Institute of Aviation Engineering，Tianjin 300300，China
  • Received:2023-04-11 Online:2024-08-01 Published:2024-08-30

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Abstract:

In order to solve the problems of slow cache scheduling and poor performance in multi-core systems， a cache scheduling algorithm optimization method for embedded multi-core systems is proposed. By establishing a multi-core system scheduling model， analyze the overall resource load balance of the system； Calculate the synchronization ratio of the system by expanding the scheduling strategy； By using integer linear programming equations， the system achieves task load balancing， minimizes communication overhead， and satisfies on-chip storage limitations， achieving cache scheduling optimization for embedded multi-core systems. The experimental results show that the proposed method has lower communication overhead and a cache scheduling time between 6.38-12.32 ms， indicating better cache scheduling performance.

Key words: embedded multi-core processor, communication overhead, data flow diagram, expand the scheduling strategy, cache scheduling optimization

CLC Number: 

  • TP391

Fig.1

Cache scheduling model for embedded multi-core systems"

Fig.2

Scheduling sequence before and after expansion"

Fig.3

Cache structure of multi-core system"

Fig.4

Comparison of reception rates under different processor cores"

Fig.5

Communication overhead and task load of the three methods"

Table 1

Cache scheduling time of three methods"

实验次数缓存调度时间（单位：ms）
处理器核数/个文献［3］方法文献［4］方法本文方法
1220.3615.6910.89
318.3114.468.75
416.3513.656.38
2219.6314.6812.32
318.6513.3311.61
417.6512.398.36
3218.9916.3811.23
317.9414.3610.69
415.6513.997.63
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