吉林大学学报(工学版) ›› 2013, Vol. 43 ›› Issue (02): 472-479.

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FPGA hardware implementation scheme for AQM algorithm

YANG Xiao-ping1,2, ZHENG Nan2, CHEN Hong1,2, WANG Ya-jun3   

  1. 1. State Key Laboratory of Automotive Simulation and Control, Jilin University, Changchun 130022, China;
    2. College of Communication Engineering, Jilin University, Changchun 130022, China;
    3. NO.32 Research Institute of China Electronics Technology Group Corporation, Shanghai 200233, China
  • Received:2011-12-05 Online:2013-03-01 Published:2013-03-01

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Abstract: The Field Programmable Gate Array (FPGA) hardware implementation scheme for Active Queue Management (AQM) algorithms was proposed in order to increase the execution speed and real-time of the algorithms, and to decrease the consumption of router resource. The serial communication programs between FPGA and the software-router IPCop were written. The scheme was applied to Random Early Detection (RED) algorithm. Test results show that the general communication interface between FPGA and the router was achieved, and the function of effective and rapid congestion control of RED algorithm was realized in the hardware level. This research provides an effective scheme for FPGA hardware implementation of the AQM algorithms.

Key words: automatic control, active queue management, field programmable gate array(FPGA), RED algorithm

CLC Number: 

  • TP24
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[4] Guan He, Yang Xiao-ping, Chen Hong, et al. Implementation of software router embedded PID AQM algorithm in the communication test network[J]. IEEE CEME International Conference, 2010, 10(25):254-257.

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